000 00319nam a2200121Ia 4500
008 211209s2006 xx 000 0 und d
020 _a8131706338
041 _aeng
100 _aYALAMACHILI, SUDHAKAR
245 _aINTRODUCTORY VHDL: FROM SIMULATION TO WYWTHESIS
260 _aNEW DELHI
_bPEARSON
_c2006
300 _a401
999 _c60708
_d60708