LOW POWER METHODOLOGY MANUAL: FOR SYSTEM -ON-CHIP DESIGN

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TextLanguage: English Publication details: NEW YORK SPRINGER 2008Description: XVI,300ISBN:

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Item type	Home library	Call number	Status	Date due	Barcode
Books	M S Ramaiah Institute of Technology	621.392 KEA/FLY (Browse shelf(Opens below))	Available		69954

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Previous	621.392 BRO FUNDAMENTALS OF DIGITAL LOGIC WITH VERILOG DESIGN	621.392 BRO FUNDAMENTALS OF DIGITAL LOGIC WITH VERILOG DESIGN	621.392 BRO FUNDAMENTALS OF DIGITAL LOGIC WITH VERILOG DESIGN	621.392 KEA/FLY LOW POWER METHODOLOGY MANUAL: FOR SYSTEM -ON-CHIP DESIGN	621.392 O08 HDL PROGRAMMING: VHDL AND VERILOG (WITH CD)	621.392 PAL VERILOG HDL: A GUIDE TO DIGITAL DESIGN AND SYNTHESIS	621.392 PAL VERILOG HDL: A GUIDE TO DIGITAL DESIGN AND SYNTHESIS	Next

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